1. Field of the Invention
The present invention relates generally to a method for producing a nonvolatile semiconductor memory device and the device itself. More specifically, the present invention relates to a method for producing a nonvolatile semiconductor memory device so as to suppress embedding failure between memory cells when an interlayer dielectric film is formed and such a device itself.
2. Description of the Related Art
A nonvolatile semiconductor memory device including memory cells is a kind of semiconductor memory device, and a floating gate electrode and a control gate electrode are stacked in each of the memory cells. A NAND-type nonvolatile semiconductor memory device is of particular interest in view of high integration, and the NAND-type nonvolatile semiconductor memory device includes a NAND-type memory cell array in which the memory cells are connected in series to share a source/drain region of each memory cell.
FIG. 1 is an equivalent circuit diagram of the NAND-type memory cell array, and FIG. 2 is a plan layout view thereof. As shown in FIG. 1, in the NAND-type memory cell array, memory cells CG1.1, CG2.1, CG3.1, . . . ,CGn.1 are connected in series and a floating gate electrode and a control gate electrode are stacked in each of the memory cells CG1.1, CG2.1, CG3.1, . . . ,CGn.1. Furthermore, a drain diffusion region of the memory cell CG1.1 at one end of the line of the memory cells is connected to a bit line BL1 via a selecting transistor SG1.1 and a bit line contact. On the other hand, a source diffusion region of the memory cell CGn.1 at the other end of the line of memory cells is connected to a source line S via a selecting transistor SG2.1 and a source line contact. These memory cells are arranged in the matrix form so as to constitute the memory cell array.
As shown in FIG. 2, each of the memory cells is formed on a common well of a semiconductor substrate. The control gate electrodes of the memory cells CG1.1, CG2.1, CG3.1, . . . , CGn.1 (CG1.2, CG2.2, CG3.2, . . . , CGn.2) are continuously formed in a direction which intersects a bit line direction so as to constitute word lines WL1, WL2, . . . , WLn. The control gate electrodes of the selecting transistors SG1.1 and SG2.2 are also continuously formed in the word line direction so as to constitute selecting lines SL1 and SL2. As shown by dotted lines, the floating gate electrodes of the memory cells are separated from one another.
Methods for producing such a nonvolatile semiconductor memory device are disclosed, for example, in Japanese Patent Laid-Open Publication No. 2002-83884, Japanese Patent Laid-Open Publication No. 2000-174145 and so on. The method for producing the nonvolatile semiconductor memory device disclosed in Japanese Patent Laid-Open Publication No. 2002-83884 will be explained in accordance with FIG. 3 through FIG. 16.
FIG. 3 through FIG. 13 and FIG. 15 are sectional views taken along the line A-A′ of the nonvolatile semiconductor memory device in FIG. 2, and FIG. 14 and FIG. 16 are sectional views taken along the line B-B′ of the nonvolatile semiconductor memory device in FIG. 2.
First referring to FIG. 3, a first silicon oxide film 102 is formed on a semiconductor substrate 100 such as a silicon substrate. The first silicon oxide film 102 constitutes a gate insulating film afterward. In this case, the first silicon oxide film 102 has a thickness of 10 nm. Thereafter, a first polysilicon film 104 is formed on the first silicon oxide film 102. In this case, the first polysilicon film 104 has a thickness of 60 nm. Subsequently, a silicon nitride film 106 is formed on the first polysilicon film 104 and a second silicon oxide film 108 is formed on the silicon nitride film 106.
Next, as shown in FIG. 4, a photoresist 110 is applied on the second silicon oxide film 108 and slits extending along the bit line direction are formed in the photoresist 110 by the photoengraving process. Subsequently, the second silicon oxide film 108 and the silicon nitride film 106 are etched by the RIE (Reactive Ion Etching) using the photoresist 110 as a mask.
Next, as shown in FIG. 5, the nonvolatile semiconductor memory device is exposed to an O2 plasma atmosphere and the photoresist 100 is removed. Thereafter, the first polysilicon film 104, the first silicon oxide film 102 and the semiconductor substrate 100 are etched using the second silicon oxide film 108 as a mask, so that grooves 112 are formed in the semiconductor substrate 100. Subsequently, the nonvolatile semiconductor memory device is heated in an oxygen atmosphere so as to form a third silicon oxide film 114. In this case, the third silicon oxide film 114 has a thickness of 6 nm. Thereafter, a fourth silicon oxide film 116 is formed so that it is embedded in the grooves 112 in the semiconductor substrate 100 by the HDP (High Density Plasma) process.
Next, as shown in FIG. 6, the fourth silicon oxide film 116 is polished and flattened by the CMP (Chemical Mechanical Polishing) method. The fourth silicon oxide film 116 is polished between the top and the bottom of the silicon nitride film 106. Thereafter, the nonvolatile semiconductor memory device is heated in a nitrogen atmosphere.
Next, as shown in FIG. 7, it is dipped into NH4F solution, and then the silicon nitride film 106 is removed by the wet etching, for example, by the phosphoric acid process at 150° C. Thereby, the third silicon oxide film 114 and the fourth silicon oxide film 116 form STI (Shallow Trench Isolation) element isolation regions.
Next, as shown in FIG. 8, a second polysilicon film 120, in which phosphorus is doped, is formed on the semiconductor device by the LPCVD (Low Pressure Chemical Vapor Deposition) method, and then the fifth silicon oxide film 122 is formed on the second polysilicon film 120. Subsequently, a photoresist 124 is applied to the fifth silicon oxide film 122, and then slits extending along the bit line direction are formed in the photoresist 124 by the photoengraving process.
Next, as shown in FIG. 9, the fifth silicon oxide film 122 is etched by the RIE method using the photoresist 124 as a mask. Subsequently, the nonvolatile semiconductor memory device is exposed to an O2 plasma atmosphere and then the photoresist 124 is removed. Thereafter, the sixth silicon oxide film 126 is formed on the semiconductor device by the LPCVD method.
Next, as shown in FIG. 10, the sixth silicon oxide film 126 is etched back so as to form sidewalls 126a on side wall portions of the fifth silicon oxide film 122. The sidewalls 126a and the fifth silicon oxide films 122 form a mask which has slits extending along the bit line direction.
Next, as shown in FIG. 11, the second polysilicon film 120 is etched by the RIE method using the sidewalls 126a and the fifth silicon oxide films 122 as the mask. Subsequently, the nonvolatile semiconductor memory device is exposed to the HF-Vapor, and then the sidewalls 126a and the fifth silicon oxide films 122 are removed. Thereby, the first polysilicon film 104 and the second polysilicon film 120 are separated in the bit line direction, and they constitute floating gate electrodes FG later.
Next, as shown in FIG. 12, an ONO (a silicon oxide film—a silicon nitride film—a silicon oxide film) film 130, which is an example of an insulating film, is formed by the LPCVD method, and then it is heated in an oxygen atmosphere. Thereafter, a third polysilicon film 132 is formed on the ONO film 130 by the LPCVD method. Subsequently, tungsten silicide (WSi) film 134 is formed on the third polysilicon film 132 by the PVD (Physical Vapor Deposition) method. Thereafter, a seventh silicon oxide film 136 is formed on the tungsten silicide film 134 by the LPCVD method. In this case, the seventh silicon oxide film 136 has a thickness of 20 nm.
Next, as shown in FIG. 13 and FIG. 14, a photoresist 140 is applied to the seventh silicon oxide film 136 and then a predetermined pattern is produced in the photoresist 140 by the photo engraving process. That is, the photoresist 140 which has slits extending along the word line direction is formed. Thereafter, the seventh silicon oxide film 136 is etched by RIE method using the photoresist 140 as a mask.
Next, as shown in FIG. 15 and FIG. 16, the photoresist 140 is removed. Thereafter, the tungsten silicide film 134, the third polysilicon film 132, the ONO film 130, the second polysilicon film 120 and the first polysilicon film 104 are etched using the seventh silicon oxide films 136 as a mask. Thereby, the tungsten silicide film 134, the third polysilicon film 132, the ONO film 130, the second polysilicon film 120 and the first polysilicon film 104 are separated in the word line direction. As a result, tungsten silicide film 134 and the third polysilicon film 132 constitute control gate electrodes CG, and the first polysilicon film 104 and the second polysilicon film 120 constitute floating gate electrodes FG. Namely, nonvolatile memory cells each of which has the floating gate electrode FG and the control gate electrode CG are formed.
Next, on both sides of the first polysilicon films 104, the second polysilicon films 120 and the third polysilicon films 132 in the word line direction, oxide films 162 which are an example of an insulating film are formed by the oxide process (RTO). Thereafter, source/drain regions 160 are formed by the ion implanting process. Subsequently, a silicon nitride film 164 which is an example of an insulating film is formed so as to cover every memory cell, and the silicon nitride film 164 has a thickness of 40 nm. Thereafter, an interlayer dielectric film 150 is formed so as to be embedded in gaps between the memory cells and so as to cover every memory cell, and then the interlayer dielectric film 150 is flattened. In this case, the interlayer dielectric film 150 is formed by the following steps. That is, the nonvolatile semiconductor memory device is heated in a nitrogen atmosphere, and an eighth silicon oxide film is formed by the oxidation process. Subsequently, a ninth silicon oxide film and a second silicon nitride film are formed by the LPCVD method. Thereafter, a tenth silicon oxide film, in which boron or phosphorus is doped, is formed, and then the nonvolatile semiconductor memory device is heated in an oxygen atmosphere. Subsequently, the semiconductor memory device is flattened, so that the interlayer dielectric film 150 is obtained.
By the way, it is preferable that the gate electrode has a wide width in order to improve characteristics of the memory cell. That is, in FIG. 16, it is desirable to expand the width W1 of the control gate electrode CG and the width W1 of the floating gate electrode FG of the memory cell. However, if the width W1 of the gate electrode is expanded, the width W2 between the gate electrodes is narrowed. As a result, it arises the problem that forming the interlayer dielectric film 150 embedded between the gate electrodes is difficult. That is, it increases the possibility that embedding failure arises when the interlayer dielectric film 150 is formed.